1. Field of the Invention
The invention relates to the field of semiconductor testing and packaging and more particularly to integrated circuit bond pad exposure, packaging, and testing.
2. Description of Related Art
In the manufacture of semiconductor devices, it is advisable that such devices be tested at the wafer level to evaluate their functionality. The process in which die in a wafer are tested is commonly referred to as xe2x80x9cwafer sort.xe2x80x9d Testing and determining design flaws at the die level offers several advantages. First, it allows designers to evaluate the functionality of new devices during development. Increasing packaging costs also make wafer sorting a viable cost saver, in that reliability of each die on a wafer may be tested before incurring the higher costs of packaging. Measuring reliability also allows the performance of the production process to be evaluated and production consistency rated, such as for example by xe2x80x9cbin switchingxe2x80x9d whereby the performance of a wafer is downgraded because that wafer""s performance did not meet the expected criteria.
FIG. 1 illustrates a surface view of the top side of an integrated circuit device. Metal interconnect lines and components of integrated circuit device 11 are formed on an underlying silicon substrate. The side of the silicon substrate on which the integrated circuit is formed shall herein be referred to as the top side of the silicon substrate. As illustrated in FIG. 1, bond pads 13 are located along the periphery of integrated circuit device 11. In the center of integrated circuit device 11 is the active region 12 containing the majority of the high density, active circuitry of integrated circuit device 11. To activate the circuitry within active region 12, it is necessary to supply voltage signals to bond pads 13. These voltage signals are supplied to bond pads 13 through a package to which integrated circuit device 11 is affixed.
FIG. 2 illustrates a cross-section of integrated circuit device 11 after packaging. After integrated circuit device 11 is affixed to package substrate 15, individual bond wires 14 are used to electrically couple each bond pad 13 to a corresponding pad on package substrate 15. Each corresponding pad 13 on package substrate 15 is then individually coupled to an external pin 16. The packaged integrated circuit device of FIG. 2 may then be placed within a socket in order to electrically couple external pin 16 to drivers that supply the necessary voltage signal to activate integrated circuit device 11. As illustrated in FIG. 2, integrated circuit device 11 is mounted to package substrate 15 with its top-side facing away from package substrate 15. In this manner, once integrated circuit device 11 is activated through package pin 16, the internal, active region 12 may be accessed and probed for testing since neither bond pads 13, package substrate 15, nor bond wires 14 obscure access to this region of integrated circuit device 11.
FIG. 3 illustrates a top-side view of a second bond pad configuration on an integrated circuit device. As illustrated in FIG. 3, bond pads 21 of integrated circuit device 20 are formed along the top of the entire integrated circuit device so that the bond pads now reside directly over the active circuitry region of integrated circuit device 20. By forming bond pads in both the center and periphery of integrated circuit device 20, more bond pads can be placed across the surface of the device than can be placed only within the peripheral region. In addition, active circuitry which underlies bond pads 21 of integrated circuit device can be directly coupled to its nearest bond pad using relatively short interconnect lines. This minimizes the resistive, capacitive, and inductive effects associated with routing interconnect lines over long distances, improving speed performance.
FIG. 4 is an illustration of a cross-section of integrated circuit device 20 after mounting to a package substrate 22. In order to mount integrated circuit device 20 to package substrate 22, solder balls 24 are placed on each of bond pads 21 to electrically couple each bond pad 21 to its corresponding pad on package substrate 22. Each corresponding pad on package substrate 22 is, in turn, coupled to an external pin 23. Integrated circuit device 20 is mounted to package substrate 22 with its top-side facing towards the package substrate. In other words, in comparison to the method used to mount integrated circuit device 11 to its package substrate in FIG. 2, integrated circuit device 20 is xe2x80x9cflipped.xe2x80x9d For this reason, the design of integrated circuit device 20 illustrated in FIG. 3 and its subsequent packaging method illustrated in FIG. 4 is referred to as flip-chip technology. The technology is also known as Controlled Collapsable Chip Connection (C4), named after the package mounting technique of using solder to replace bond wires.
Integrated circuit device 11 (as shown in FIG. 1) or integrated circuit device 20 (as shown in FIG. 3) illustrate bond pads 13 and 21, respectively, available for electrical coupling to a corresponding pad on package substrate, 15 and 22, respectively. In general, after the device is made, bond pads 13 and 21, respectively, lie beneath dielectric layers and must be exposed for bonding to package 15 and 22, respectively. In the typical process, bond pads 13 and 21, respectively, are covered by a hard passivation layer of, for example, silicon nitride (Si3N4). This hard passivation layer is covered by a soft passivation layer of, for example, a photodefinable polyimide. The hard and soft passivation layers protect the device from the ambient, for example, scratches, moisture, and impurities.
FIGS. 5-8 illustrate the prior art process for exposing bond pads 13 or 21, respectively. FIG. 5 shows an integrated circuit structure 50 with bond pad 55 overlying structure 50. Examples of conventional bond pads include aluminum (Al), aluminum-copper (Alxe2x80x94Cu) alloy, aluminum-copper-silicon (Alxe2x80x94Cuxe2x80x94Si) alloy metal bond pads. Overlying bond pad 55 is hard passivation layer 60, such as for example, Si3N4. Above Si3N4 layer 60 is a soft passivation layer 65, such as for example, a photodefinable polyimide passivation layer. FIG. 5 illustrates the first processing step of exposing bond pad 55 to a light source. In this step, a portion 70 of photodefinable polyimide layer 65 is protected from light exposure. The remaining photodefinable polyimide layer 65 is exposed to ultraviolet light and developed. During development, the unexposed region of photodefinable polyimide layer 65 is dissolved, exposing Si3N4 hard passivation layer 60 in that area.
FIG. 6 shows the second step in the prior art process of exposing the integrated circuit bond pad. In FIG. 6, the exposed Si3N4 layer 65 is etched to remove Si3N4 from an area above bond pad 55. A suitable etchant is, for example, a NF3/He and SF6/He etch chemistries.
Once bond pad 55 is exposed, the wafer is cured through a pad cure step as shown in FIG. 7. The pad cure step cures the remaining photodefinable polyimide layer 65. The curing step also results in degassing/outgassing of particles from polyimide layer 65, in part, particles resulting from the prior Si3N4 etching step, to form on bond pad 55. Further, the curing step is a high temperature cure which oxidizes a portion of bond pad 55. Thus, for example, oxidized aluminum metal becomes alumina or sapphire which forms a hard coating on bond pad 55. FIG. 7 shows oxidized and particle residual layer 70 formed on bond pad 55. In order to bond a suitable package wire to bond pad 55 or to test the integrated circuit at bond pad 55, residual layer 70 must be diminished or removed. Thus, FIG. 8 shows a cleaning step of a sputter etch that is typically used to remove residual layer 75 to expose bond pad 55. Since the oxidized particle-deposited bond pad residual layer 70 is generally hard, the sputter etch must be significant to diminish residual layer 70.
To effectively bond a bond pad to a package, a portion of the bond pad surface must be free of residual particles and oxide formation. Therefore, great care must be practiced to expose a portion of the metal surface of the bond pad.
Wafer testing and sorting typically involves the use of probing technology wherein a probe card containing probe features engages the bond pads on a die so as to connect the pads to a circuit tester. FIG. 9 illustrates a typical testing apparatus including a tester 75, test head 76, and handler 77, that is used to test the performance of a die on a wafer. As illustrated, probe card 72 sits below and in contact with test head 76. During testing, the handler 77 supports the wafer on platform (chuck) 78 and positions the wafer so as to precisely align the bond pads of a die to be tested with the probe features on the probe card. Chuck 78 is connected to a staging device 79. Staging device 79 typically positions chuck 78 along an X-Y plane by moving along a stage floor 73 on a ball screw stage assembly. Staging device 79 may also position chuck 78 by floating above stage floor 73 on a magnetic air bearing. Chuck 78 typically includes a vacuum chuck wherein the wafer being tested is held in position by drawing a vacuum within a plurality of interconnecting channels that are formed within the surface of chuck 78. Once aligned, chuck 78 is raised such that the bond pads of the die are forced against the probe features on the probe card.
When testing a wafer, it is often hard to prevent the oxidation of the aluminum bond pad surface prior to testing. Therefore, most categories of probing or testing utilize some form of xe2x80x9cscrubxe2x80x9d at the touch-down phase of a probe feature to a bond pad. Scrub applies to the process where the probe features on a probe card pierce (scrub) the layer of oxide that grows quickly on an exposed aluminum bond pad, despite a previous exposure by, for example, a sputter etch. Generally, scrub applies to the destruction of any non-conductive layer that produces a barrier between the test probes of a probe card and the base metal of a bond pad. The purpose of the scrub is to break through the non-conductive layer on the bond pad in order to establish a good electrical contact between the probe features and the base metal of the bond pad. Scrub occurs when the components of the handler forces the wafer, and subsequently, the bond pads of a die, against the probe features on the probe card causing the probe features to deflect and the non-conductive layer to break. The scrub is generated by a small horizontal movement of each probe feature across the surface of each corresponding bond pad as the probe features deflect. As the probe features move across the bond pad, they break and penetrate the non-conductive oxide layer thereby establishing a good electrical contact between the probe features and the bond pads. This type of scrub is referred to as xe2x80x9cpassivexe2x80x9d scrub. Typically, the amount of deflection of the probe features, and, hence, the amount of scrub achieved, is proportional to the force applied by the movement of the wafer against the probe card features. The additional movement of a wafer toward a probe card after initial contact with a probe feature is known as xe2x80x9coverdrive.xe2x80x9d
Probe cards currently available are generally of the passive scrub type. The multilayer cantilever tungsten needle probe card 80, as illustrated in FIG. 10 via a cross-sectional view, is one example. As schematically shown in FIG. 10, probe card 80 possesses a printed circuit board 81 with tungsten needles 82 extending out from probe card 80. In general, a ceramic support ring 84 is inserted into a counterbore in printed circuit board 81 on which probe needles 82 are held in position by an epoxy ring 88. Each needle 82 contains a tip or probe feature 83 for making contact with the bond pads of a die. As previously discussed, the amount of scrub (or horizontal displacement) achieved on the surface of a bond pad is proportional to the vertical displacement applied by the movement of the wafer against the probe card features. Probe card 80 is referred to as a multilayer probe card, because probe card 80 has multiple layers of probe needles 82 extending from epoxy ring 88 to accommodate existing integrated circuit device densities, i.e., existing pad pitches.
FIG. 10 illustrates that in prior art configurations, epoxy ring 88 has a vertical sidewall from which probe needles 82 extend. FIG. 10 also illustrates that probe needles 82, including probe tips 83 have a common beam length (LB) and extend from epoxy ring 88 at a common beam angle.
A tungsten needle probe card, as illustrated in FIG. 10, typically requires overdrive levels of 0.002 to 0.004 inches to achieve good electrical contact at the bond pads. Thus, tungsten needle 82 must be of sufficient dimensions, e.g., diameter, beam length, etch length (which determines the tapered geometry), and extrinsic durability to break through an oxide layer present on a bond pad.
FIG. 11 shows an expanded view of a portion of the multilayer probe card of FIG. 10 with three needles 82 extending out from epoxy ring 88, each needle or beam 82 containing a tip or probe feature 83 for making contact with the bond pads of a die. FIG. 11 also shows epoxy ring 88 having a vertical sidewall from which beams 82 extend. In order to accommodate existing pad pitches under 100 microns, beams 82 are generally stacked or layered in epoxy ring 88. FIG. 11 shows a probe assembly having three layers of probe needles or probe beams. The stacking or layering of beams 82 allows adjacent pads of reduced dimensions to be tested while maintaining the mechanical integrity of beams 82 in epoxy ring 88. Prior art probe cards, as illustrated in FIG. 11, use beams 82 of precisely the same length (LB) and extending away from epoxy ring 88 at precisely the same beam angle xcex8B, such as for example 7xc2x0. Prior art probe cards also use probe tips 83 of different vertical length (LT), such as for example in FIG. 11, tips 83 of 8 mils, 18 mils, and 25 mils. Variable tip length yields inconsistent scrub lengths.
There are number of problems associated with the passive scrub cantilever needle probe card and the scrubbing process. First, the high overdrive levels required to achieve good electrical contact between the probe features and bond pads cause the probe features to bend, break, and wear more quickly, resulting in increased replacement and repair costs. Another problem is that it sometimes requires two or more touch-downs per die test to break through the pad oxidation layer. This prolongs the amount of time to perform a die test and it diminishes the effective life of a probe card. Yet another problem with passive scrub needle cards is that stray particle and oxide buildup often occur at the tip of the probe features. Stray particle and oxide buildup contributes to high contact resistance between the probe feature and bond pad and electrical shorts between the probe needles. High contact resistance causes inaccurate voltage levels during device testing due to the voltage produced across the probe tip. This may cause a device to incorrectly fail a test resulting in lower test yields and, for example, bin switching, i.e., the recharacterization of device performance based upon testing results. Thus, the oxidation of the bond pads and the methods for scrubbing the pads to effectively test the device present many problems that hamper consistent testing or probing of wafers.
As noted above, as device densities increase on a die, the number of bond pads also increases. The common way this is accomplished is by placing the bond pads closer together, thus decreasing the pad pitch, i.e., the distance between the center of adjacent pads. Current technologies have a typical pad pitch above 80 microns. With pad pitches of 100 microns or more, conventional probe card designs have been able, with varying consistency, to scrub and make contact to the bond pad surface. This is so because the probe feature is of sufficient dimension, e.g., diameter and durable enough to break through the oxide layer and scrub the bond pad. As the pad pitch continues to decrease, sufficiently durable probe features may not be able to accommodate the smaller feature size, i.e., the probe features may not be able to get in the vicinity of the bond pad to scrub the bond pad surface. Accordingly, the probe feature must itself get smaller dimensioned and less durable to accommodate a reduced pad pitch. A less durable probe feature, however, will have difficulty breaking through an oxide layer and scrubbing the bond pad surface.
A method of exposing a bond pad of an integrated circuit is disclosed. The method includes providing an integrated circuit having a bond pad, a first passivation layer overlying a top surface of the bond pad, and a second passivation layer overlying the first passivation layer, removing a portion of the second passivation layer to expose an area of the first passivation layer above the area portion of the bond pad, curing the second passivation layer, and etching a portion of the exposed area of the first passivation layer to expose the top surface of the bond pad. A method of coupling an integrated circuit chip to a chip package is also disclosed as is a method of probing the bond pads of an integrated circuit.
A probe card is further disclosed. In one embodiment, the probe card includes a probe assembly coupled to a printed circuit board, the probe assembly having a sloped sidewall portion with a plurality of probing beams extending from the sidewall portion.
Additional features and benefits of the invention will become apparent from the detailed description, figures, and claims set forth below.